1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
As downsizing of transistor elements advances, a so-called short-channel effect becomes a problem. As a method of avoiding this short-channel effect, an elevated source/drain structure is conventionally known.
FIG. 26 is a schematic view showing a semiconductor device having an elevated source/drain structure according to prior art. As shown in FIG. 26, a gate electrode 3 is formed on a silicon substrate 1 via a gate oxide film 2, and a metal silicide layer 4 is formed on the gate electrode 3. A gate sidewall oxide film 14 and sidewall insulating film 16 are formed on the side surfaces of the gate electrode 3. The gate oxide film 2 is removed from the surface of the silicon substrate 1 outside the sidewall insulating film 16, and epitaxially grown silicon layers 20 are formed above the substrate surface position (indicated by the dotted lines in FIG. 26). An element serving as an impurity is ion-implanted into the silicon layers 20, and activation annealing is performed, thereby forming elevated source/drain diffusion layers 17.
In the above prior art, ion implantation is performed through the silicon layers 20 formed above the substrate surface position, so the source/drain diffusion layers 17 can be made shallow. Accordingly, this semiconductor device having the elevated source/drain structure can avoid the short-channel effect.
Unfortunately, this prior art has the problem that an overlap capacitance C between the gate electrode 3 and the source/drain diffusion layer 17 increases, and this decreases the operating speed of a transistor Tr. In addition, the number of fabrication steps increases, and this increases the device cost. Furthermore, a high-temperature step of epitaxial growth deteriorates the characteristics of the transistor Tr.
Note that prior art reference information related to the invention of this application is, e.g., U.S. Pat. No. 6,335,251.